1. The Field of the Invention
The present invention relates to an apparatus for processing signals detected by sensors incorporated in a power train (i.e., vehicle drive system including an engine) mounted in a vehicle, and in particular, to an apparatus for processing signals detected by sensors to sense operating states of the power train, the processing including the digitalization of the detected signals.
2. Related art
Recent vehicles which are available in the market are mostly provided with power train control systems to control their drive systems (i.e., power trains such as engines). Japanese Patent Laid-open publication No. 7-19104 discloses such a power train control system, in which analog signals detected by sensors sensing operating states of a drive system are digitized into digital data by an A/D converter and the digital signals are directly transferred to a memory via a DMA (Direct Memory Access) controller.
In other words, the power train control system is ordinarily configured such that it operates using a microcomputer as the main device. Thus when the microcomputer takes in signals detected by the sensors via an A/D converter, the DMA controller is used to lessen a calculation load to be imposed on a central processing unit (CPU).
By the way, in this conventional power train control system, the digital data which has been transferred from the DMA controller to the memory is then subjected to digital processing executed by the CPU. The digital processing includes removal of noise contained in the detected signals and analysis of waves of the detected signals.
In cases where the detected signals are required to undergo higher-precision digital possessing which includes analyzing waveforms of signals from knock sensors for determining a knocking phenomenon of an engine, it is conceivable that the digital processing at the CPU is performed using floating-point arithmetic.
Due to the fact that the floating-point arithmetic handles the floating-point type of digital data expressed by both a mantissa part consisting of a line of values of each digit and an exponent part indicating the position of the decimal point, the floating-point arithmetic has a wider range in numerals to be expressed. In contrast, fixed-point type of digital data has a decimal point fixed at a specific digit. Thus, compared to the fixed-point type of digital data, the floating-point arithmetic is much more precise. This is why the CPU uses the floating-point arithmetic for applying the digital processing to the detected signals.
Actually however, the digital data transferred from DMA controller to the memory is a fixed-point type of data produced by the A/D converter. Thus, in order to allow the CPU to apply the floating-point arithmetic to the digital data, it is required to convert the digital data from the fixed-point type of data to the floating-point type of data.
Accordingly, if such a conversion is imposed on the CPU, the load of processing which should performed by the CPU is obliged to increase. In addition, the number of accesses to the memory also increases, thus causing an excessive duty (i.e., load) of the memory bus due to having access to the memory. It is also imaginable that this excessive duty of the memory bus becomes an obstacle to the other types of processing to be executed by the CPU, such as processing for controlled variables for driving an engine.
To be more specific, the detected signals (that is, digital data which has been A/D-converted by the A/D converter) are converted in its format from the fixed-point type to the floating-point type through the processing executed by the CPU, and the conversion involves transferring data from the DMA controller to the memory, reading data from the memory by the CPU, and writing converted data into the memory by the CPU. That is, access to the memory is required three times. In particular, in the case that digital data requires to be A/D-converted at a shorter sampling period for digital processing at higher speed, the memory will be subject to frequent access based on the above three-time manner. Hence the bus to the memory is almost always occupied with accessing data and subsequent steps of data conversion. This results in a concern that the CPU cannot perform the various types of remaining processing in a steady manner.